(1) FIELD OF THE INVENTION
The present invention relates to the fabrication of semiconductor integrated circuits, and more particularly to the use of processing steps to improve the yield of semiconductor integrating circuits.
(2) DESCRIPTION OF PRIOR ART
Processing steps designed specifically to improve the manufacturing yield in semiconductor integrated circuits are used extensively. In U.S. Pat. No. 5,376,235 to Langley, a method to eliminate corrosion in conductive elements is disclosed wherein a wash in a dilute phosphoric acid, performed after metal etch, removes corrosive contaminants. A method to remove residual materials in the manufacture of semiconductor devices is shown in U.S. Pat. No. 5,578,163 to Yachi, where ashing and wet washing processes are used to achieve the removal. U.S. Pat. No. 5,668,411 to Hong et. al. shows a diffusion barrier trilayer that minimizes the reaction of a metallization layer with underlying barrier layers of integrated circuits, thus maintaining the sheet resistance of the metallization layer. Rinsing with water after tungsten etchback, but before exposure to oxygen, improves the connection between tungsten plugs and metallization layers, according to U.S. Pat. No. 5,730,834 to Gabriel. A method for improving the electrical resistance of contacting surfaces in via holes is disclosed in U.S. Pat. No. 5,736,458 to Teng, where it is shown that a N2 treatment, preferably followed by a vacuum break, results in reduced contact resistance.
The present invention relates to so-called antifuse devices. An antifuse is placed in series with a device, such as a transistor, when that device is required to be open circuited until, possibly, some future time. As inserted an antifuse acts as an insulating element, blocking current flow. When it is desired to activate the devise in series with the antifuse, a stress is applied, which causes the antifuse to become conducting and, thus, the device to become operational.
An antifuse particularly relevant to this invention is described with the aid of FIGS. 1-5 Prior Art, which depict a conventional process flow for this device. In FIG. 1 Prior Art is shown a metal plug, 12, through a layer of dielectric, 10. The material of the plug is often tungsten, although other metallic substances can be used, and the purpose of the plug is to provide electrical connection to conducting regions disposed under the plug and dielectric layer. As shown in FIG. 2 Prior Art, a blanket layer of amorphous silicon, 14, about 700 angstroms thick, is deposited followed by the blanket deposition of about 250 angstroms of TiN, 16. An etching step follows in which the amorphous silicon and TiN are removed except in a region over the metal plug and a segment of the dielectric layer adjacent to the plug, as depicted in FIG. 3 Prior Art. There follows blanket depositions of about 1000 angstroms of TiN, 18, and about 8000 angstroms of aluminum copper. 20 or an appropriate thickness of other metallization. This is depicted in FIG. 4 Prior Art. The final step is to etch these layers except in a region overlapping the amorphous silicon and TiN layer previously etched, resulting in the structure shown in FIG. 5 Prior Art.
If only potentials less then about 8 volts are applied across these layers the amorphous silicon should behave as an insulator with a very high resistance. With a voltage stress larger than about 8 volts a transition should occur and the resistance becomes and stays low. It is believed that under the influence of a sufficiently high electric field, titanium from the TiN reacts with the amorphous silicon to form titanium silicide, which is a conductor. The potential required to attain the lowest field capable of forming silicide is termed the programming voltage and the resulting silicide is called the programming silicide. The programming voltage generally depends on the materials and geometry of the device; a programming voltage of eight volts being appropriate for the typical case described and depicted in the figures. For successful operation of the antifuse it is important that the programming voltage not vary appreciably from its design value.
A source of variation of the programming voltage from its intended value is found to be photo misalignment, which could occur when defining the patterns to be etched. Structures that are sometimes observed, resulting from photo misalignment, are similar to that shown in FIG. 6 Prior Art. Programming voltages for such structures are found to be about 5 volts, which is likely to be unacceptable. Apparently, the electric field induced phenomena responsible for the transition of the amorphous silicon from insulating to conducting behavior acts more efficiently at the bare, and possibly contaminated, surface than in the bulk of the amorphous silicon. For an aligned device the bare surface of the amorphous silicon is situated away from the tungsten plug. Therefor, during voltage application, the surface field for an aligned device is smaller than the field in the bulk of the amorphous silicon that is over the tungsten plug. As a result the phenomena leading to the conducting state takes place in the bulk of the amorphous silicon, even though the susceptibility is greater at the surface. However, the surface field is larger the closer the surface is to the tungsten plug. At some distance the susceptibility advantage at the surface evens out the field advantage of the bulk and at closer distances the transition to the conducting state occurs at the surface and with a minimum applied potential, or programming voltage, lower than when the transition occurs in the bulk. Therefor, when voltage is applied across an antifuse that is misaligned as in FIG. 6 Prior Art, with the amorphous silicon surface being over the tungsten plug the electric field along the surface is comparable to that in the bulk of the amorphous silicon. In this situation the programming voltage should be near its lowest value. A value of about 5 volts is observed which is appreciably lower than the programming voltage of about 8 volts observed for an aligned antifuse.
In terms of the proposed mechanism, in which the transition to a conducting state occurs because titanium silicide forms in the amorphous silicon, the increased susceptibility can be understood because atoms can usually move much easier along a bare surface than in the bulk. This is especially the case if the surface is contaminated, as is possible to occur during processing. An enhanced reaction rate is than expected for the production of programming silicide and therefor a decreased programming voltage. A reduced programming voltage can lead to devices being activated unintentionally, and thereby causing errors. A possible solution is to increase the size of the amorphous silicon layer, and also the TiN and aluminum copper layers, relative to that of the tungsten plug. The increase should be large enough, so that even with the most severe misalignment that needs to be considered, the silicon surface is sufficiently separated from the tungsten plug so that no reduction in programming voltage takes place. However, such a solution involves an increase in the area required for the antifuse, which is clearly undesirable. Therefor, an alternative method to eliminate the occurrence of reduced programming voltage is required and is supplied by this invention.
Another configuration of the antifuse, also due to misalignment, that could lead to a reduced programming voltage is shown in FIG. 7 Prior Art. The cause of failure in this case is an increased electric field. As shown in FIG. 7 Prior Art, the bottom of the amorphous silicon sidewall is situated closer to the tungsten plug than the upper surface of the amorphous silicon, and the TiN is contacting the sidewall. The magnitude of the electric field along a field line from a lower point of the sidewall to the plug, 22, could, for this configuration, be substantially greater than the field along a field line from the top amorphous silicon surface to the plug, 24. In this case, the programming voltage would be decreased to the voltage at which the average field along a field line like 22 is equal to the average field along a field line like 24, for an aligned antifuse at the programming voltage.
Accordingly, it is a primary objective of the invention to provide a method for fabricating an antifuse that could retain its programming voltage even for quite severe misalignments. The invention provides a technique to sufficiently reduce the susceptibility of the amorphous silicon surface so that transitions to a conducting state will not occur there at voltages less than the programming voltage appropriate for the bulk of the amorphous silicon. In addition, the technique serves to prevent low voltage transitions to a conducting state caused by enhanced fields resulting from misalignment. Therefor, misalignments do not, essentially, lead to failure in antifuses fabricated according to the invention, thus increasing the antifuse process window.
In accordance with the objectives of the invention a misalignment tolerant antifuse is achieved by forming native oxide on exposed amorphous silicon surfaces, after, both, the amorphous silicon and metal etching steps. This serves to decrease the transition susceptibility at the surface to a value probably lower than that for bulk amorphous silicon and also to block the transition at regions of high electric field resulting from misalignment.
Therefor, methods of forming an antifuse according to this invention incorporate oxidation of the exposed amorphous silicon surface. A partially processed semiconductor wafer is provided, containing at least one device electrically connected to a conducting region extending almost to the wafer surface, where the conducting region is surrounded by a dielectric layer which reaches the wafer surface. A blanket layer of amorphous silicon is deposited followed by deposition of a thin blanket layer of TiN and these layers are etched down to the dielectric surface except for that above the conducting region and some of the surrounding dielectric. A thin native oxide is formed over the exposed surface of the amorphous silicon. This is followed by deposition of a thicker TIN layer and of a metallization layer, which are patterned and etched so that contact is made to the lower layers. The oxidation step is repeated so as to oxidize any amorphous silicon surface that may have been inadvertently exposed in the last etching step.